A high degree of circuit irregularity exists in the control sections of microprocessor units. Various strategies have been used in the past to automate the layout of these control sections as much as possible. Standard cell design styles and programmable logic arrays (PLAS) are two conventional approaches. The standard cell design style is however in general restricted to static gates, and further has a relatively poor density in the finalized design due to large routing area.
All conventional standard cells are fabricated using static CMOS gates. It would be impossible or highly impractical to fabricate dynamic domino logic using them, although standard cells can be used to fabricate registers and state machines. Even here, the standard cell approach suffers from low layout design densities and relatively poor speed and timing performance.
The PLA design style does not allow the free mix of static and dynamic gates without a large cost penalty in terms of layout area.
Another design style is the Weinberger array, as pioneered by A. Weinberger in "Large Scale Integration of MOS Complex Logic," IEEE Solid State Circuits, Vol. SC-II, pp. 182-190 (December, 1967). A Weinberger array comprises a plurality of elongate gate regions formed at a face of a semiconductor substrate, and interconnected by a plurality of conductors running orthogonally to the gate regions.
Recently, the Stanford Weinberger Array Minimizer and Implementor (SWAMI) logic design system has been disclosed in C. Rowen and J. Hennessy, "SWAMI: A Flexible Logic Implementation System," IEEE Twenty-second Design Automation Conference, pp. 169-175 (1985). The SWAMI logic implementation system generates multi-level logic expressions from an algorithmic description of a combinational function. The combinational function includes NAND and NOR expressions. The SWAMI Weinberger implementation is however limited to NMOS technology. Further, the Weinberger array methodology does not allow the mixture of dynamic and static gates, and is unable to incorporate such circuit structures as buffers or registers.
U.S. Pat. No. 4,319,396 issued to Law et al. discloses a gate-matrix method for fabricating insulated gate field-effect transistor (IGFET) circuits, wherein a plurality of static gate transistors are formed at selected intersections of rows and columns in an array, each row having a single gate conductor and each column forming vertical borders for the transistor source and drain regions formed therein. The columns are spaced from each other to provide spacing between horizontally adjacent transistors. A plurality of vertical conductors make connection to the source and drain regions and are insulatively spaced from the gate conductors. Law et al. however show only a logic array that is not capable of implementing dynamic logic functions.
Therefore, a need has arisen in the industry for a logic layout synthesis system that can implement functions with such non-Boolean components as dynamic domino gates, registers, buffers and precharge clocks with good final design density.